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Fig. A word-organized memory with non-destructive
read-out and equipment for erasing and writing.
and on the relevant column wires a damped
sinusoidal current-wave is sent, the highest amplitude of
which is below that corresponding to the knee in
the 0-signal curve obtained in the erasing process.
The frequency of the damped oscillation should be
considerably lower than the frequency of the
readout pulses unless some form of synchronization is
introduced. The core at the point of coincidence is
driven to a minor loop through the combined effect
of the two currents, whereas the state of the other
cores remains unchanged.
In order to get the 1-signal as high as indicated in
fig. 2 the time for writing of 1 must be rather long,
about 100 times the cycle time of the read-out pulses;
somewhat depending upon the duration of the
readout pulses, material and so on. A shorter time for
writing 1 in the order of approximately the
switching time of the material can be obtained by the
application of a pulse which tends to switch the
core, but either is interrupted before the core is
completely switched or is so weak that the core is
not too strongly magnetized in the opposite
direction. The principle is possible but has disadvantages
as regards tolerances and other respects.
References
1. Papouijs A: The Non-destructive Read-out of Magnetic Cores.
PIRE, Vol. 42, No. 8, 1954.
2. Rajciimann J A, Lo A W: The Transfluxor — a Magnetic Gate
with Stored Variable Setting. RCA Rev. Vol. 1G, June 1955.
3. Thoresen R, Ahsenaui.t W R: A New Non-destructive Read for
Magnetic Cores. Proc. Western Joint Comp. Conf., March 1955.
4. Winnow B: A Radio Frequency Non-destructive Read-out for
Magnetic Core Memories. IRE Trans., Vol. F.C-3, Dec. 1954.
5. Newhouse V L: The Utilization of Domain Wall Viscosity in
Data-handling Devices. PIRE, Vol. 45, No. 11, 1957.
A Linear Selection Memory with Transistor
Driving Circuits
Bengt Jiewertz, SAAB, Linköping
l uppsatsen beskrives ett minnessystem av
ordvalstyp med tillhörande kretsar för transistordrivning.
I ett experimentellt utförande med S4-kärnor har
erhållits en minnescykel av 4 /us. Effektförlusten hos
drivkretsar och grindar vid en arbetstemperatur av
60°C diskuteras. Upptagning av karaktäristiska
kurvor för ferritkärnor med en drivmetod där man
använder en polariserande ström visar att ett
ordvalssystem kan arbeta vid mycket högre temperatur än
60° C.
The read and write currents on the wires through
the core matrices of a coincident current memory
give, due to wire inductance and cores, back
voltages at the rise and fall of the current pulses. These
peak voltages are of such an amplitude that they
are comparable to transistor operating voltages. The
maximum collector-emitter voltage and the back
voltage peaks thus limit the value of the useful drive
voltage.
In a linear selection memory the drive wires only
run through a number of cores equal to the number
of bits of a word which reduces the back voltage
amplitude1. A linear selection memory is then
more suitable for short memory cycles with short
rise and fall times of the pulses. Some other
advantages as compared to a coincident current memory
621.318.042 : G81.14
are lower power consumption, higher signal to noise
ratio on the information wire, easier threading of
the cores without a diagonal wire. With asymmetric
operation round the hysteresis loop of the cores it
is also possible to operate a linear selection memory
at a higher speed and temperature than a coincident
current memory.
The basis of this design has been to use only
transistors in the selection and drive circuits to examine
how the drive currents and the switching speed
affects the dissipation power of the transistors. The
main disadvantage is that several transistors must
be connected in parallel because of their limited
power dissipation. This together with a number of
diodes in the read and write wires makes the price
of a linear selection system about 50 per cent higher
than a coincident system of the same size.
Description of a linear selection system
A linear selection memory with n x n words of m
bits is seen in the block diagram of fig. 1. Here are
shown some word wires with memory cores, address
gates, drive current generator and read amplifiers
with help current drivers. The address register with
row and column decoders are omitted. To minimize
the number of the address selection circuits these
are arranged in n rows and n columns each with
ELTEKN IK 1959 1 0]
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